搜索资源列表
usb_verilog.tar
- 文件包含一个usb 专用集成电路设计项目，用的verilog 原码-document contains a usb ASIC design, the original code verilog
USB_I2C_MAC_FPGA_Code
- 《FPGA数字电子系统设计与开发实例导航》的配套光盘，Verilog编写，USB、I2C、MAC的接口设计-"FPGA digital electronic system design and development examples navigation" matching discs, Verilog prepared, USB, I2C, the MAC interface design
verilog_usbblaster
- 用verilog编写的USB下载线程序 实现USB协议和JTAG接口的数据转换实现状态机
FT245_R_W
- USB芯片FT245BM读写代码,在Quartus II V7.2上测试成功!---Verilog语言.
usb_funct.tar
- Verilog语言描述的USB 2.0接口和新功能固件。
usbfree_core
- 完整的usb freecore，全部用verilog编写
FT245BM
- 这是一个在MAX II CPLD利用FT245BM 模块实现USB传输的读写程序，用的是Verilog HDL语言
logic
- SRAM和USB芯片FT245的VERILOG逻辑控制
USB_jtag
- 用verilog编写的USB下载线程序 实现USB协议和JTAG接口的数据转换实现状态机。
usb1.1
- USB 1.1的verilog代码，已通过fpga验证
Verilog_CY7C68013-SLAVE-FIFO
- 用VERILOG 编写 CY7C68013 usb数据采集SLAVE FIFO模式驱动程序 ，已验证过-Prepared with the VERILOG CY7C68013 usb data acquisition SLAVE FIFO mode driver, has proven
H.264
- 详尽地论述了H.264 特点、编码器原理、解码器原理、编解码器的实现。为了更好地理解H.264 编解码原理及其实现，第7 章详细介绍了H.264 码流的句法和语义。最后对H.264 视频编码传输的QoS 进行了专门地论述。-H.264 are discussed in detail the characteristics of the principle of encoders, decoders principle, the realization of codec. To better un
USB2.0
- usb2.0 fpga程序 用vhdl语言编写 quartus环境实现 -usb2.0 fpga using vhdl language program quartus environment to achieve
USB_LOOP
- 该Verilog程序基于USB芯片68013,FPGA50T,实现了两台电脑之间使用两个68013和一个FPGA50T来通信-Verilog program is based on the USB chip 68013, FPGA50T, realized between two computers using two 68013 and one FPGA50T to communicate
usb1.1
- USB 1.1的verilog代码，已通过fpga 程序源代码内容-Verilog code for USB 1.1, has passed through the contents of the source code fpga
Verilog_USB_OUT
- USB out，使用Verilog写的，包含完整工程、文档和USB芯片的固件-USB OUT, VERILOG, Including project、document，USB firmware
Verilog_USB_IN
- USB in 模型，作为输入，包括基于Altera的工程、源码、固件，使用Verilog-USB in model, as input, including the Altera-based project, source code, firmware, Verilog
USB_FPGA
- 基于Cyclone EP3C25的USB与CY60183传递数据的FIFO Verilog HDL源代码（FPGA端程序）-The program is a communication source code about USBCyclone EP3C25 transfering data via FIFO with CY60183 (only FPGA source code(verilog HDL) is included)
USB_Core
- USB Core in Verilog for implementation into FPGA devices.
68013iologic
- 该代码是verilog语言。是USB接口芯片68013的ioFIFO描述。-The code is the verilog language. 68013 ioFIFO descr iption of the USB interface chip.